1. Field of the Invention
The present invention refers to a process for manufacturing integrated devices having connections on a separate wafer, and to an integrated device thus obtained.
2. Description of the Related Art
As is known, standard processes for manufacturing integrated circuits involve carrying out individual process steps in a sequential way. The manufacture of micro-integrated structures (so-called micro-electromechanical systems, or MEMS) and their control circuits in a same monolithic device has required a certain number of manufacture steps for defining the micro-integrated structures within the process of manufacturing traditional electronic components, with an increase in complexity which is not always sustainable. Consequently, in many cases the choice is made to carry out parallel manufacturing processes to obtain, on one hand, the control circuits, and, on the other, the micro-integrated structures, and at a certain point to bond the obtained structures, so that the two processes may involve only a few non-critical common steps.
Thereby, it is possible to continue to exploit the potential of planar technology (batch-type processes), whilst the minimum time required for obtaining a finished device (so-called “cycle time”) is markedly reduced. In addition, with parallel processing, it is possible to separate parts and processing steps that could lead to contamination.
Recently a manufacturing process has been proposed (see U.S. Pat. No. 5,736,395) based upon parallel manufacture of a first substrate housing an integrated circuit and a second substrate comprising the interconnections for the integrated circuit, and bonding the two substrates together in the final manufacturing steps.
The separation of the operations for forming the integrated components in a silicon substrate from the operations for forming interconnections enables a simplification of the process as a whole.
In the parallel process proposed, bonding of the two substrates is obtained by forming, on both substrates, appropriate metal contact regions coated with a bonding layer of a low-melting alloyable metal, for example gold or palladium.
The need to include steps for depositing and defining the metal contact regions and the bonding layer on top of both substrates is, however, disadvantageous in so far as it does not enable separation of the operations for forming components integrated in the silicon from the metallurgical operations for forming interconnections. Consequently, the techniques for forming the interconnections risk affecting the components that belong to the integrated circuit and may give rise to undesired charging phenomena or to contamination.
In addition, the described parallel process requires forming through holes in the substrate carrying the interconnections for aligning the two substrates in the bonding step, with an increase in costs and in manufacturing times for forming the corresponding masks and the holes.